TIER IV has joined the Japan Science and Technology Agency’s Next-Generation Edge AI Semiconductor Research and Development Program and intends to open-source the logic design, compiler, and toolchain for an AI chip built to run inference for end-to-end Level 4 autonomous driving. The chip is being developed to support Autoware, the open-source autonomous driving software stack the company leads, and will be evaluated as part of a software-defined system-on-chip. Under the JST program, a research team led by Professor Yoshihiro Kawahara of the Graduate School of Engineering at The University of Tokyo will pursue use-case-driven, functionally differentiated physical AI chip design, while TIER IV handles the logic design.
Highlights
- Program participation: TIER IV joins JST’s Next-Generation Edge AI Semiconductor R&D Program, with the University of Tokyo team led by Professor Kawahara covering functionally differentiated chip design
- Open-source scope: logic design, compiler, and related toolchain are all slated for release, extending the Autoware model from software to silicon
- Intermediate representation: the Tensor Operator Set Architecture (TOSA) sits between AI models and hardware, allowing model changes to be absorbed through compiler and runtime updates
- Power envelope: the design targets deployment from embedded devices operating at several watts to in-vehicle electronic control units operating at several tens of watts
Why Does Level 4 Need a Different Compute Approach?
High-performance computing hardware, GPUs in particular, has carried the recent acceleration in AI. Level 4 autonomous driving imposes a different constraint set: models must run continuously under real-world, real-time conditions. TIER IV frames the requirement as complementing existing high-performance computing rather than replacing it, while advancing power efficiency alongside adaptability, transparency, and verifiability.
Power Efficiency Built Around Transformer Inference
Autonomous driving AI increasingly leans on large-scale Transformer models that handle camera images and point cloud data in an integrated path from perception through motion planning. The architecture concentrates on Transformer inference and simplifies the control mechanisms that general-purpose computing requires.
Data needed for model execution is placed in advance and reused repeatedly on-chip, cutting power spent on external memory transfers and computation control. Dedicated compute circuits handle operations common to Transformers, including matrix multiplication and attention mechanisms. TIER IV says the objective is performance per watt across the full autonomous driving system, including Autoware, rather than peak chip performance in isolation.
TOSA Layer Decouples Models From Hardware
Architectures tied to a specific model or hardware configuration struggle to keep pace with a shifting AI landscape. TIER IV’s answer is TOSA, a standardized intermediate representation inserted between AI models and the chip.
Operations from models built in frameworks such as PyTorch convert into a common TOSA representation, with optimization and code generation performed through TOSA before execution. The result is loose coupling between frameworks and hardware — changes in model architecture or computational method can be handled largely through software updates to the compiler and runtime, without a full chip redesign.
Open-Sourcing the Logic Design and Toolchain
In safety-critical applications, the internal architecture and processing flow of the computing system matter as much as the model itself. TIER IV will publish the logic design together with the compiler and toolchain, allowing semiconductor manufacturers and developers to inspect the chip’s internal architecture and software behavior, then modify, extend, and reuse it against their own vehicle platforms, models, performance requirements, and power constraints.
The stated goal is an ecosystem in which autonomous driving AI advances without dependence on specific semiconductor products or closed development environments.
Formal Verification of Model Transformations
Running an AI model on a chip involves format conversion, computational optimization, quantization, and rounding. Those steps improve performance and efficiency but can introduce numerical differences that affect final results.
Using TOSA’s defined operator specifications as a base, TIER IV will structure the compilation transformation process and apply formal verification techniques. For selected transformations and operations, the initiative aims to mathematically verify numerical consistency before and after transformation and compliance with predefined error tolerances — making the transformations traceable and the resulting processing verifiable.
Executive Commentary
“As Level 4 autonomous driving moves toward broader deployment, we believe the next step is to complement these platforms with computing architectures designed for real-world and real-time requirements. Through this initiative, we are introducing a software-defined and open approach to AI chip design that combines power efficiency, adaptability, transparency and verifiability. By extending the open-source philosophy behind Autoware from software to AI chip design and related toolchains, we aim to create an open ecosystem in which automakers, semiconductor manufacturers and developers can build upon the technology and continue advancing their own systems,” said Shinpei Kato, founder and CEO of TIER IV.
“In physical AI applications such as robotics and autonomous driving, GPU power consumption has long been a major bottleneck for deployment on battery-powered devices. This project aims to fundamentally overcome this constraint through a functionally differentiated chip design backward-mapped from specific use cases. This initiative, supported by an open ecosystem, has the potential to lay the foundations for a steady stream of Japanese startups creating high-value semiconductors,” said Professor Yoshihiro Kawahara of the Graduate School of Engineering, The University of Tokyo.
